Gemini Deep Research agentは、複数ステップのリサーチタスクを自律的に計画し、実行から統合まで進めるエージェントです。 長時間の情報収集と要点の統合に最適化されており、「調べてまとめる」をアプリケーション側へ組み込みやすくなったと言えるでしょう。さらにレポートは引用文献付きで出力可能。
Gemini Deep Research agentはGemini 3 Proを搭載し、Web検索とユーザーのデータを使って複雑な情報をリサーチしてくれます。リサーチでは反復的な検索と読み取りが走り、完了までは数分かかるため、バックグラウンド実行で開始し、結果をポーリングして受け取る運用が前提になります。
Gemini Deep Research agentの仕組み
Gemini Deep Research agentは単一の生成処理ではなく、計画と実行を分離した設計が採用されており、「入力して即応答」という従来のLLM利用とは異なります。
まずGemini Deep Research agentの中心となるのは、ユーザーから与えられた調査テーマを複数のサブタスクへ分解するプロセスです。
Gemini Deep Research agentは高機能なリサーチエージェントである一方、万能ではない点を理解しておくことが重要です。
導入判断では「何ができるか」だけでなく「どこに限界があるか」にも目を向ける必要があるでしょう。
まず、安全性の観点では、Deep Research agentがアクセスする情報源が明確に定義されています。デフォルトでは公開Web上の情報を対象としており、google_searchやurl_contextを通じてデータを取得します。そのため、クローズドなデータベースや認証が必要な情報には直接アクセスしません。
では実際にGemini Deep Research agentを実装していきます。Interactions API経由での利用となります。
まずは必要ライブラリのインストール。
!pip -q install -U google-genai
コードを実行するにあたり、GEMINIのAPIキーが必要になるので、まだ取得していない場合にはGoogle AI Studioから取得してください。
サンプルコードはこちら
import time
from google import genai
API_KEY = "YOUR_GEMINI_API_KEY_HERE"
client = genai.Client(api_key=API_KEY)
interaction = client.interactions.create(
input="Research the history of Google TPUs.",
agent="deep-research-pro-preview-12-2025",
background=True
)
print("Research started:", interaction.id)
while True:
interaction = client.interactions.get(interaction.id)
if interaction.status == "completed":
print(interaction.outputs[-1].text)
break
if interaction.status == "failed":
print("Research failed:", interaction.error)
break
time.sleep(10)
結果はこちら
/tmp/ipython-input-1644205629.py:10: UserWarning: Interactions usage is experimental and may change in future versions.
interaction = client.interactions.create(
Research started: v1_ChduNVk3YWFuMkxLVzZfdU1QenJydnVRcxIXbjVZN2FhbjJMS1c2X3VNUHpycnZ1UXM
# The History and Evolution of Google Tensor Processing Units (TPUs): From Internal Crisis to the Age of Inference
### Key Points
* **Origins in Necessity:** The TPU project was initiated in 2013 after Jeff Dean calculated that enabling voice search for all Android users would require doubling Google's global data center footprint if relying on standard CPUs.
* **Architectural Divergence:** Unlike GPUs, which rely on massive parallel threading (SIMT), TPUs utilize **systolic arrays**, a design that mimics the flow of blood through the heart to maximize data reuse and minimize memory access energy costs.
* **Generational Trajectory:** The lineage began with **TPU v1 (2015)** strictly for inference, pivoted to training with **TPU v2 (2017)** and **v3 (2018)**, introduced optical switching in **TPU v4 (2021)**, and bifurcated into efficiency and performance lines with **TPU v5 (2023)**.
* **Recent Innovations:** The **TPU v6 (Trillium)** and **TPU v7 (Ironwood)** represent a return to inference optimization ("The Age of Inference"), featuring massive High Bandwidth Memory (HBM) capacities and native FP8 support to handle generative AI models.
* **Ecosystem Impact:** The development of the TPU necessitated the creation of the **bfloat16** numerical format, now an industry standard, and the XLA (Accelerated Linear Algebra) compiler.
---
## 1. Introduction: The Computational Crisis of 2013
The history of the Google Tensor Processing Unit (TPU) is not merely a story of silicon fabrication, but a narrative of architectural survival. By the early 2010s, the slowing of Moore’s Law collided violently with the explosive computational demands of deep learning.
In 2013, a pivotal internal projection catalyzed Google's hardware strategy. Jeff Dean, a Google Senior Fellow, and his team performed a "back-of-the-envelope" calculation regarding the company's emerging voice search capabilities. They estimated that if every Android user utilized voice search for just three minutes per day, the computational load of the requisite speech recognition models would compel Google to double its global data center capacity [cite: 1, 2].
This projection revealed that General Purpose Graphics Processing Units (GPGPUs) and Central Processing Units (CPUs) were insufficient for the specific mathematics of deep learning at Google's scale. CPUs were too slow due to the Von Neumann bottleneck, and GPUs, while powerful, consumed excessive energy for the specific matrix operations required by TensorFlow. Consequently, Google initiated a secretive "crash program" to design a Domain Specific Architecture (DSA) optimized exclusively for machine learning [cite: 3, 4]. The result was the TPU, an Application-Specific Integrated Circuit (ASIC) that would remain a trade secret until its unveiling in 2016.
---
## 2. Architectural Philosophy: The Systolic Array
To understand the evolution of the TPU, one must understand the fundamental divergence in its design philosophy compared to CPUs and GPUs. The core innovation of the TPU is the **Systolic Array**.
### 2.1 The Von Neumann Bottleneck vs. Systolic Execution
In traditional CPU and GPU architectures, the Arithmetic Logic Units (ALUs) fetch data from memory, perform an operation, and write the result back to memory (registers or cache). For matrix multiplication—the primary operation in neural networks—this results in a massive "Von Neumann bottleneck," where energy and time are wasted moving data back and forth.
The TPU utilizes a systolic array architecture, a concept dating back to HTK and Charles's 1983 patent and research by H.T. Kung [cite: 5, 6]. In a systolic array, data flows through a grid of ALUs like blood through a heart (hence "systolic").
* **Weight Stationary:** Model weights are pre-loaded into the array and stay stationary.
* **Data Flow:** Activation data flows in from one direction, interacts with the weights, and partial sums are passed directly to the next ALU in the sequence without writing back to memory [cite: 4, 7].
This design allows the TPU to perform tens of thousands of multiply-accumulate (MAC) operations per cycle with significantly reduced power consumption compared to the "fetch-decode-execute" cycle of general-purpose processors [cite: 6].
---
## 3. TPU v1: The Inference Pioneer (2015–2016)
**Status:** Inference Only
**Process:** 28nm
**Clock Speed:** 700 MHz
Deployed internally in 2015 and announced at Google I/O 2016, the first-generation TPU was a single-purpose accelerator designed strictly for **inference**—the process of running a trained model to make predictions [cite: 8, 9].
### 3.1 Specifications and Performance
The TPU v1 was built on a 28nm process and ran at 700 MHz. It featured a massive **256 × 256 systolic array** capable of performing 8-bit integer (INT8) operations.
* **Throughput:** It could execute 65,536 multiply-accumulate operations per cycle, translating to approximately **92 TeraOps/second (TOPS)** [cite: 6].
* **Memory:** It utilized 28 MiB of on-chip software-managed memory (Unified Buffer) to minimize off-chip access.
* **Interface:** It connected to the host server via a PCIe Gen3 x16 bus, functioning as a coprocessor similar to a floating-point unit (FPU) [cite: 10].
### 3.2 Impact
The TPU v1 was instrumental in Google's dominance in AI services. It powered Google Search (RankBrain), Google Translate, and the AlphaGo system that defeated Lee Sedol in 2016 [cite: 11]. In production workloads, it demonstrated **15x to 30x faster performance** and **30x to 80x better performance-per-watt** than contemporary CPUs (Haswell) and GPUs (NVIDIA K80) [cite: 12, 13].
---
## 4. TPU v2: The Training Pivot (2017)
**Status:** Training and Inference
**Introduction:** Cloud TPU
**Key Innovation:** bfloat16, HBM
While v1 solved the inference crisis, training large models remained a bottleneck. Training requires higher precision than inference (to capture gradient descent nuances) and significantly more memory bandwidth. In 2017, Google unveiled TPU v2, a complete redesign aimed at training [cite: 13].
### 4.1 Architecture Changes
* **Floating Point Support:** Unlike v1's integer-only math, v2 introduced support for floating-point calculations.
* **bfloat16 (Brain Floating Point):** Google introduced a custom numerical format, bfloat16. It retained the range of a standard 32-bit float (FP32) but reduced the precision (mantissa) to 16 bits. This allowed for the speed of half-precision computing without the loss of dynamic range that often caused training to diverge in standard FP16 [cite: 13].
* **Systolic Array Reconfiguration:** The single 256x256 array of v1 was replaced by **two 128x128 MXUs (Matrix Multiply Units)** per core. This provided better utilization for smaller batch sizes [cite: 13].
* **High Bandwidth Memory (HBM):** To feed the training workload, v2 incorporated 16 GB of HBM per chip, providing 600 GB/s of bandwidth [cite: 3, 10].
### 4.2 The TPU Pod
TPU v2 introduced the concept of the **TPU Pod**. Using a custom Inter-Chip Interconnect (ICI), 64 TPU v2 devices (256 chips) could be connected into a 2D torus topology, functioning as a single supercomputer with 11.5 petaFLOPS of performance [cite: 10]. This allowed Google to offer "Cloud TPUs" to external customers for the first time.
---
## 5. TPU v3: Liquid Cooling and Density (2018)
**Status:** High-Performance Training
**Key Innovation:** Liquid Cooling
Announced in May 2018, TPU v3 was an evolutionary step focused on power density and thermal management. As Moore's Law slowed, increasing performance required pushing power limits.
### 5.1 Specifications
* **Performance:** TPU v3 delivered roughly **2x the performance** of v2, achieving roughly 100 petaFLOPS per pod [cite: 14].
* **Memory:** HBM capacity was doubled to 32 GB per chip.
* **Thermal Engineering:** The chips ran so hot that Google implemented **liquid cooling** directly to the chip within the data center racks—a first for Google's massive-scale infrastructure [cite: 8, 14].
### 5.2 Pod Scaling
The v3 Pods were scaled up to **1,024 chips**, offering an 8-fold increase in total system performance compared to v2 Pods [cite: 10]. This generation solidified the TPU's role in training massive models like BERT.
---
## 6. TPU v4: The Optical Revolution (2021)
**Status:** Warehouse-Scale Supercomputing
**Key Innovation:** Optical Circuit Switching (OCS), SparseCores
TPU v4, announced in 2021, marked a radical shift in data center networking. It was designed to solve the connectivity bottlenecks inherent in scaling to thousands of chips.
### 6.1 Optical Circuit Switching (OCS)
Previous TPU generations used electrical cables for the Inter-Chip Interconnect (ICI). TPU v4 introduced **Optical Circuit Switches (OCS)**. These MEMS-based mirrors could physically reconfigure the network topology in milliseconds [cite: 13, 15].
* **Dynamic Topology:** The OCS allowed the system to route around failed chips dynamically and change the topology (e.g., 3D torus, twisted torus) to suit specific model architectures [cite: 15, 16].
* **Scale:** A single v4 Pod contained **4,096 chips**, delivering over 1 exaFLOP of compute power [cite: 14].
### 6.2 SparseCores
TPU v4 publicly disclosed the existence of **SparseCores**—specialized dataflow processors integrated into the TPU die. While present since v2, they were formally detailed with v4. SparseCores are optimized for **embeddings** (common in recommendation systems), accelerating these specific workloads by 5x–7x while occupying only ~5% of the die area [cite: 15].
### 6.3 Performance
TPU v4 offered a 2.1x performance increase over v3 and a 2.7x improvement in performance-per-watt [cite: 15]. It was manufactured on a 7nm process node [cite: 10].
---
## 7. TPU v5: Bifurcation and Specialization (2023)
In 2023, Google acknowledged that the AI market had split into two distinct needs: cost-effective training/inference and massive-scale frontier model training. Consequently, the TPU line bifurcated.
### 7.1 TPU v5e (Efficiency)
Launched to target the "efficiency" segment, TPU v5e was optimized for performance-per-dollar.
* **Design:** It returned to a smaller physical footprint with **one TensorCore per chip** (down from two in v4) and utilized a 2D torus topology [cite: 13].
* **Specs:** 197 TFLOPS (BF16) and 16 GB HBM2 [cite: 17, 18].
* **Use Case:** Ideal for inference and training mid-sized models where cost is the primary constraint.
### 7.2 TPU v5p (Performance)
Announced later in 2023, v5p was the "performance" variant designed to compete with the NVIDIA H100.
* **Specs:** 459 TFLOPS (BF16) and **95 GB of HBM** per chip [cite: 19].
* **Scaling:** It supported massive scalability, with pods containing up to **8,960 chips** [cite: 13].
* **Interconnect:** It utilized a high-speed 3D torus topology with 4,800 Gbps of ICI bandwidth per chip [cite: 13].
---
## 8. TPU v6 (Trillium): The Efficiency Powerhouse (2024)
Announced in May 2024, the sixth generation, codenamed **Trillium** (also referred to as v6e), focused on maximizing the "bang for the buck" and energy efficiency for the Gemini era.
### 8.1 Key Specifications
* **Performance:** Trillium delivers a **4.7x increase in peak compute performance** per chip compared to TPU v5e [cite: 17, 20].
* **Memory:** HBM capacity and bandwidth were doubled compared to v5e (32 GB HBM per chip) [cite: 17, 21].
* **Matrix Units:** Trillium expanded the MXU size back to **256 x 256**, quadrupling the FLOPs per cycle compared to the 128x128 design of v5e [cite: 13].
* **Energy:** It achieved a 67% increase in energy efficiency over v5e [cite: 20].
Trillium was designed to be the "most flop-dense TPU to date," capable of scaling to building-scale supercomputers using Google's Jupiter data center network [cite: 20].
---
## 9. TPU v7 (Ironwood): The Age of Inference (2025)
Unveiled in April 2025, TPU v7, codenamed **Ironwood**, marks a strategic pivot back to the roots of the TPU: inference. However, unlike v1, Ironwood is designed for *generative* inference—running massive "thinking models" like Gemini 2.5 and Claude [cite: 22, 23].
### 9.1 The "Age of Inference"
Google executives described Ironwood as the hardware for the "Age of Inference," where AI agents proactively generate insights rather than just responding to queries. This requires massive memory and low latency [cite: 23, 24].
### 9.2 Technical Specifications
* **Memory:** A staggering **192 GB of HBM** per chip (6x that of Trillium) [cite: 25, 26]. This allows entire large language models to fit on fewer chips, reducing latency.
* **Compute:** 4,614 TFLOPS (FP8) per chip [cite: 19, 25].
* **Precision:** Ironwood is the first TPU to feature native **FP8 (8-bit floating point)** support, optimizing for the lower precision requirements of inference without sacrificing model quality [cite: 3, 27].
* **Power Efficiency:** 2x performance-per-watt compared to Trillium [cite: 22].
* **Scale:** Ironwood pods can scale to **9,216 chips**, delivering 42.5 ExaFLOPS of FP8 compute [cite: 23].
### 9.3 SparseCore Evolution
Ironwood includes 3rd-generation SparseCores (4 per chip) to handle the embedding-heavy workloads of recommendation systems and large vocabulary LLMs [cite: 19].
---
## 10. Edge TPU: AI for the IoT (2018–Present)
While Cloud TPUs dominated the data center, Google identified a need for local processing on Internet of Things (IoT) devices.
* **Launch:** Announced in July 2018 under the **Coral** brand [cite: 10].
* **Specs:** The Edge TPU is a small ASIC capable of **4 TOPS** (trillion operations per second) while consuming only **2 Watts** of power [cite: 10].
* **Application:** It allows devices (cameras, sensors, Raspberry Pis) to run TensorFlow Lite models locally, preserving privacy and reducing latency by avoiding cloud round-trips [cite: 28, 29].
---
## 11. Comparative Analysis: TPU Generations
The following table summarizes the evolution of the Cloud TPU specifications.
| Feature | TPU v1 | TPU v2 | TPU v3 | TPU v4 | TPU v5p | Trillium (v6e) | Ironwood (v7) |
| :--- | :--- | :--- | :--- | :--- | :--- | :--- | :--- |
| **Year** | 2015 | 2017 | 2018 | 2021 | 2023 | 2024 | 2025 |
| **Primary Focus** | Inference | Training | Training | Scale | Performance | Efficiency | Inference |
| **MXU Size** | 256x256 | 128x128 (x2) | 128x128 (x2) | 128x128 (x4) | 128x128 (x2) | 256x256 | 256x256 |
| **Precision** | INT8 | BF16 | BF16 | BF16 | BF16 | BF16 | FP8 / BF16 |
| **HBM/Chip** | N/A (SRAM) | 8 GB | 16 GB | 32 GB | 95 GB | 32 GB | 192 GB |
| **Peak TFLOPS** | 92 (TOPS) | 45 | 123 | 275 | 459 | 918 | 4,614 (FP8) |
| **Interconnect** | PCIe | 2D Torus | 2D Torus | 3D Torus (OCS) | 3D Torus | 2D Torus | 3D Mesh |
| **Max Pod Size** | N/A | 256 chips | 1,024 chips | 4,096 chips | 8,960 chips | 256 chips | 9,216 chips |
*Note: Data compiled from sources [cite: 8, 10, 13, 19, 20, 25]. TFLOPS values refer to bfloat16 unless otherwise noted.*
---
## 12. Software Ecosystem: The Hidden Half
The hardware evolution of the TPU is inextricably linked to its software. The complexity of the systolic array required a compiler capable of managing data flow with extreme precision.
* **XLA (Accelerated Linear Algebra):** A domain-specific compiler that optimizes linear algebra computations. It "fuses" operations to prevent the TPU from writing intermediate results to memory, maximizing the efficiency of the systolic array [cite: 30].
* **Frameworks:** Initially built for **TensorFlow**, the TPU ecosystem has expanded to support **JAX** and **PyTorch** (via PyTorch/XLA), broadening its adoption among researchers [cite: 10, 31].
---
## 13. Conclusion
The history of the Google TPU is a testament to the power of vertical integration. By controlling the entire stack—from the datacenter architecture (liquid cooling, OCS) to the chip design (systolic arrays, SparseCores) and the software (TensorFlow, XLA)—Google successfully navigated the end of Moore's Law.
From the crisis-driven inception of **TPU v1** to the massive, inference-optimized **Ironwood (v7)**, the TPU has evolved from a niche accelerator into the backbone of the modern AI economy. As generative AI models continue to grow in size and complexity, the TPU's trajectory suggests a continued focus on memory bandwidth, optical interconnectivity, and specialized precision formats like FP8 to sustain the "Age of Inference."
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17. [hpcwire.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQH02UtWEvvCoyNNDMj28UxnpOES0Zk6NGTwWhIt2tfk_qkyzxXphXOhGSD-B8eS3GMBAkgSq9sEMsfm7whZCwJdU44WhJC9bAIuFAnntUb69wFcwTJLbZaNsmqWO1Get3WT0RsUAizT4OlHAsY7M-rUeEd8RsMA_1dQhoXKaFkmaUNE3b2wBiL8lz6rqm36D0OKI9GNrCKCEPBWY96Q_k9o)
18. [hpcwire.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQEhfNQLRddZ_efP0gSpVAWY1MCA57JbP_Mk4YXa6fzdtUhiQsyZhXqbiy5HlWwT98OBqN_xpeWrg34Dei5NaQRDpqvjDJmJM3SZjC8BZpTZJwkny7JZNZCk3oSwKTKBOibmsEx9eK5mF1nYPj6yEbJS4RRaJ5u-LCXYnYLY4nVIEY7VVlmMCzIVSvcJmioA0BLQ13xi43PsSZ8=)
19. [google.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQGpn0k7zqO0yrMityVvSErBtb0_5kzGMicTY5bctSMvZVRjZckln4Vi4NeRCHsKPEzZN72p_cryf7agiD0DCubGGZGMIlxUfrshpK79OCk6tXdM3QTw_Cs5TUxvYhlrRZNTkA==)
20. [google.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQENCjo7XSxz4Sc4HZAARHFN8bi6zNbQLE9pMoledY_8rY-LXt817OZabzZOge2tUO8GahrQH1erZzZOBWNwmVe5fIzJ5slLFraYyU9_4vtLOFyxasqs2qoIq1eWsE3SiyKs-p3KcocJ3nuO4-n7eHkxadzhzfi8BHwoqFY35gCHOWIwlAxXihgKzeQIzijypQ0=)
21. [reddit.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQHGhXmIOy5Y8ZC8GqJgEYhtipkzV36n1_bybnxV75OJPZq-ux85dmcvUkYnyc1FEJs9C0DPwuqpHOvqDp_oKQlL7dORAq3RWwXuEu0VYWlBvQKuObJrCSb1Y2j-u2p66yZGhzUQBGrqL8_5JmBKFHStXLdSJmnCzRn63DVUzl5i-LVU9Z-_lTDPlGyb8iCsmpU=)
22. [creativestrategies.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQEMn6h4m2f0ww8-DMGoBwB1L68IzhYg-mev0e6_cGxIVDJFx_t-1_eIACVg_Z0kZI3TAo_R6jZJETSbp3aYBve4CPNv5ZgHpGOQe8JLoOVyIq9vtyO9bZpJX7nVq12ZwqtZAm0ardQ4u4RAzjLxHM-14ldmYVvuzIrQ4ZS9rQ7zddxRqOUQSGHbdsZeUzB0DUuQd5cROEPMjjB0H261tqdEktT6RtRhxzNLijzLk8kpyQ==)
23. [blog.google](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQF1tdGp1tS3tKFOL7imMGNYK5reIlN7v_DJKbKard8wdygPy2NXheMAakJ7EoiARI35qSEJylngUGefYiroq3mef325u8labMxiBe2dHuL6Qur8U7fZghjtEFZeHIJpYMZGYjhByw2YjqDvoex48rBZWNjHB7zRXzf94I5H9Z4=)
24. [workmind.ai](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQHDDFqpd_fvrcFmaiQC8BvX1EaqM7Mk8r8DhznIViUfrF702upiOpt2-Ez0q3WaT0Wv7365_E0ekMq0KBUECfQo75mQq4rMeSEEo94F6EgVrDpD88HoDGaDwMqrr-Zsmo19bZO55NaYR-ej9bPbyBjeGBP-UhP1lKVcgQ22grcBheNdP-I4gA==)
25. [insidehpc.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQE1INUE1jWqlcuB8BB3CuHSKR4hsIbiaKkDYDnH9d0ElUpNDaYwUGPzXGSlc6uJlAxh1eqnwcOWauUxNzDBU-am2ml7aZC_8RsDeL0A8DEcIOwVtunhfB-I-8_EeZ76pJrm65SRcE1Ggacv9SV5nipPRGsa9fFeYJOb)
26. [techpowerup.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQE8-qc0lIjhLmWHwfjpy3m33ugc5W5BIvxA9bNOGlmuoDLQtzysc_PA-p-B9Fg3qCpNo0A4U-gDy0tdAv4yWZAxTY98pEkHiuijikBOgibxNRJYdFJG5J3mF_rIMqS3eB6XsuEtl1PBZogihpTX6kaf5uG27H_pT8nu182zyCNls1K748dvZMOSbiJmXgyY1fY=)
27. [nextplatform.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQE_NdTFiL3OijlTUOK5WYg_4HHs44AZEmUjDlUk5pLNSsxuRNz_0phHDRnMOTC4uF4W70nRLuZifX9ZzE_Ymc8i2m2xO2HnA_IcrtHwVolq6C6dL2x0vVC1lbFXM_vDXsiiSVdXNw3R1Jj8mKRQJUFNKe62klOQS5jkgYrmvHiMSe8ODsU7S6mTkKSdeolSiWtNX-K2dfQfvyN-MWuCmg==)
28. [viso.ai](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQHauwKcTMEgNKVyvaduhhrU_xFPb-sCcV5g9iDrJzCKoaSAPA1KE3G2-QA5gUwU70c7NBtKph_NgP_zgoV91daXeHbwRFrG26Fg8z71P1msZibXnet0pZ7UK_q9)
29. [assured-systems.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQF4St0UVZpk0CN4ylSY6EJJPzP7u6eeVoPnwdpfVlRTiQELl7HrWcl5vOpjS3j0HaQywc3SZMIHziYhOyIq2O89TJ2mBq4gdycVETeLUW4orIbIrhaXtuIP_eYkX_5L42OMYLtFw9M9DweKEC1JRS98zUuSl2fw6EBXkvoygQyn7vOhr4li3A==)
30. [google.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQGrTiW5zOaLlOGhQ0NNlyi_woe_9o13A92aj2sQOtAd32NLeA0qi-QwJedOIf7t5CUx2Ry-Z1o1gUc_2a5P9XS6asLzpjgeUdwREv2eLjQZEnXyvL0fEPqv1c6dewpV7Ug4S-N-6dcDuYKtx24UxAzUtALd0hNZGg==)
31. [google.com](https://vertexaisearch.cloud.google.com/grounding-api-redirect/AUZIYQEKkgG06JD25q_dbdfmkbXqGaWnc08TRKrD47OvjTX_l2QWG11K-d1EoPsehgTebk4JHq8mWQ5iOMIzGk94ksobj4yOZMN6RGFrjVw8PYshImZITPGyYrViPswreFBndxtc5zSkcIUsrRo=)
レイアウトなどを整えていないので、見た目はイマイチな感じですが、Marpのレイアウトを作っておき、Gemini Deep Research agentに与えるプロンプトももう少し工夫をすれば、資料作成があっという間に終わりそうです。
まとめ
本記事ではGemini Deep Research agentの概要から仕組み、実際に使ってみた所感について解説をしました。これまでGeminiはあまりリサーチ系が得意ではない…といった声が聞かれていましたが、Gemini Deep Research agentによって、リサーチもGeminiに任せられるようになるかもしれませんね。
ぜひ皆さんも本記事を参考にGemini Deep Research agentを使ってみてください！
最後に
いかがだったでしょうか？
リサーチや調査レポートの精度を高めたい方は、Gemini Deep Research agentの活用してみてはいかがでしょうか。
